1. Technical Field
The technical field relates to a semiconductor memory device having a cross-point type memory cell array in which a plurality of memory cells comprising variable resistive elements that store information by an electric resistance change are arranged in the direction of rows and columns respectively, and one ends of the memory cells in the same row are connected to the same selected row line and the other ends thereof in the same column are connected to the same selected column.
2. Description of the Related Art
Recently, a cross-point type semiconductor memory device (referred to as the “cross-point memory” occasionally hereinafter) in which a memory cell does not comprise a selecting element except a memory element and a memory cell array is formed such that the memory element directly connects a selected row line (referred to as the “word line” hereinafter) to a selected column line (referred to as the “bit line” hereinafter) has been developed (refer to Japanese Unexamined Patent Publication No. 2002-8369).
According to “Method of Detecting Equivalent Voltage for Resistive Cross-point Memory Cell Array” disclosed in the Japanese Unexamined Patent Publication No. 2002-8369, a predetermined voltage is supplied to each word line and bit line to detect a resistance state of the memory cell of an MRAM Magnetic Random Access Memory). According to the Japanese Unexamined Patent Publication No. 2002-8369, when a selected memory cell is read, the resistance state, that is, the memory state of the selected memory cell is detected by applying a first voltage to the selected word line and applying a second voltage lower than the first voltage, to the selected and unselected bit lines and the unselected word lines.
In addition, this cross-point memory has a hierarchy structure in which the memory cell array is divided into a plurality of banks, a local bit line of each bank is connected to a global bit line through a bank select transistor and a local word line of each bank is connected to a global word line through a bank select transistor.
FIG. 7 shows the circuit constitution of a conventional cross-point memory cell array, and set levels of supply voltages and current pathways to the word line and the bit line. According to the cross-point memory shown in FIG. 7, when a selected memory cell is read, the resistance state of the memory cell selected on the side of the word line is detected by applying a voltage V1 to a selected bit line and applying a voltage V2 higher than the voltage V1, to selected and unselected word lines and unselected bit lines.
FIG. 7 shows a case where when the resistance state of the memory cell at the crossed point between the word line D0 and the bit line B0 is read, the desired resistance state of the memory cell is determined by reading the current of the selected word line D0.
FIG. 8 shows another example of voltage setting for each word line and each bit line and current pathways when the resistance value of the memory cell positioned at the crossed point between the word line D0 and the bit line B0 is read. According to FIG. 8, similar to the voltage setting disclosed in the above Japanese Unexamined Patent Publication No. 2002-8369, when the selected memory cell is read, the resistance state of the memory cell selected on the side of the bit line is detected by applying a voltage V1 to the selected word line and applying a voltage V2 lower than the voltage V1, to the selected and unselected bit lines and the unselected word lines. In this case, the desired resistance state of the memory cell is determined by reading the current of the bit line B0.
FIG. 9 shows a current flow when a word line drive circuit to drive the word line and a bit line drive circuit to drive the bit line are connected to the memory cell array shown in FIG. 7 and the reading is executed.
According to this reading operation, a word line drive circuit shown in FIG. 10 is connected to each word line, so that the voltage V2 is applied to each word line by the word line drive circuit. Furthermore, a bit line drive circuit shown in FIG. 11 is connected to each bit line, so that the voltage V1 is applied to the selected bit line B0 connected to the selected memory cell to be read and the voltage V2 is applied to the unselected bit lines except the selected bit line B0 by the bit line drive circuit.
In addition, since all resistances (memory cells) connected to the selected bit line B0 are accessed in this reading operation, the reading current flows in all resistances connected to the selected bit line B0. The reading current flows from each word line and concentrates on the selected bit line B0 through each resistance connected to the selected bit line B0. The reading current concentrating on the selected bit line B0 is connected to the circuit to apply the voltage V1 through a bank select transistor SelB0, a switch circuit SW1 and an access bit line driver B0Dr connected to the selected bit line B0. In this case, the reading current concentrating on the selected bit line B0 raises the voltage between the source and drain of the bank select transistor SelB0 when it passes through the bank select transistor SelB0. The larger the reading current flowing in the selected bit line B0 is or the higher the ON resistance of the bank select transistor SelB0 is, the larger the rise range of the voltage is.
In the reading operation shown in FIG. 9, when the resistance values of the memory cells connected to the selected bit line B0 are all low, the reading current flowing in the selected bit line B0 is largest. Therefore, the rise range of the voltage in the bank select transistor SelB0 is largest.
Oppositely, in the reading operation shown in FIG. 9, when the resistance values of the memory cells connected to the selected bit line B0 are all high, the reading current flowing in the selected bit line B0 is smallest. Therefore, the rise range of the voltage in the bank select transistor SelB0 is smallest.
Here, it is assumed that the ratio of the resistance value when the resistance value of the memory cell is high and when the resistance value is low is 5. Furthermore, as shown in FIG. 9, when the resistance values of the memory cells connected to the selected bit line B0 are all low, it is assumed that the current value flowing in the selected bit line is set to a bit line current IBOL. In addition, as shown in FIG. 9, when the resistance values of the memory cells connected to the selected bit line B0 are all high, it is assumed that the current value flowing in the selected bit line is set to a bit line current IBOH. In this case, the current ratio between the bit line current IBOL and the bit line current IBOH is shown by the following formula 1.IBOL/IBOH=5  (1)
Therefore, when it is assumed that the bank select transistor SelB0 operates in a linear region, the voltage rise through the bank select transistor SelB0 connected to the selected bit line B0 is such that the voltage rise range ΔVL when the resistance values of the selected memory cells are all low is 5ΔVH that is five times as large as the voltage rise range ΔVH when the resistance values of the memory cells connected to the selected bit line B0 are all high.
When the reading operation is executed in the cross-point type memory cell array as shown in FIG. 9, the resistance value, that is, the memory state of the selected memory cell to be read is determined by measuring the current value in the word line drive circuit. However, the measured current value largely depends on the voltage applied to the selected memory cell.
When it is assumed that the voltage rise generated through the bank select transistor SelB0 and the voltage drop caused by the wiring resistance of the selected bit line are 0V in FIG. 9 or 7, the voltage level Vbiasc applied to the memory cell is as shown in the following formula 2.Vbiasc=V2−V1  (2)
However, when the resistance values of the memory cells connected to the selected bit line B0 are all low as shown in FIG. 9, since the voltage rise range ΔVL is not 0V but 5ΔVH as described above, the voltage level Vbiasc applied to the selected memory cell is shown as the following formula 3 in an actual case.Vbiasc1=V2−V1−5ΔVH  (3)
In addition, as shown in FIG. 9, when the resistance values of the memory cells connected to the selected bit line B0 are all high, the voltage level Vbiasc2 applied to the selected memory cell is shown as the following formula 4.Vbiasc2=V2−V1−ΔVH  (4)
Here, the measured current in the word line drive circuit is proportional to the voltage level applied to the memory cell. Thus, when the voltage rise range ΔVH and 5ΔVH on the selected bit line are large enough to be compared with the voltage difference V2−V1 between the word line and the selected bit line, the voltage difference between the voltage level Vbiasc2 applied to the selected memory cell when the resistance values of the memory cells connected to the selected bit line B0 are all high, and the voltage level Vbiasc1 applied to the selected memory cell when the resistance values of the memory cells connected to the selected bit line B0 are all low is shown as the following formula 5.Vbiasc2−Vbiasc1=V2−V1−ΔVH−(V2−V1−5ΔVH)=4ΔVH  (5)
That is, even when the selected memory cell showing the same resistance value is accessed, the current difference proportional to the voltage difference 4ΔVH is generated as the measured current difference in the word line drive circuit, so that a reading current margin is decreased for that.